ECE 368---CAD Based Logic Design

Instructor: Prof. Shantanu Dutt

Important Information:

1. M/W/F 2-2:50pm, 219 TH. 
   
   
2. Instructor's office hrs (930 SEO): W 5:30-6:30 pm, F 3:30-4:30 pm. 
   
   
3. TA: Soumya Banerjee, [e-mail] 
   TBA 
   
   
4. Before the next lecture, remember to always go through the material covered in the previous lecture and make sure you understand it all. Ask Qs to TAs and me during office hours, and possibly in the next lecture. 
   
   
5. Always do the given reading assignment for the class in which it will be needed. This way you'll get the most out of that lecture; otherwise you may not understand much of it. The reading assignments generally cover background material from pre-requisite courses or some nitty-gritty details like program syntax that are self explanatory. 
   
   
6. Syllabus: pdf 
   
   
7. A possible VHDL PC software along with an introductory VHDL tutorial: VHDL s/w and tutorial link 
   
   
8. Other useful VHDL sources: 
   
   (1) VHDL FAQs, etc. 
   
   (2) On-line resources of the Ashenden textbook 
   
   
9. Quartus Schematic Capture Based Simulation Tool: pdf 
   
   
10. VHDL Language Reference Manual: Not available at this time 
    
    
11. Lecture Notes 
    
    
12. Lab instructions for setting up the Synopsys VHDL software and running it (for your lab assignments) (pdf). 
    IGNORE html instr as indicated (pdf is more recent version) + Source codes. 
    
    
13. X Windows simulation tool (courtesy of Kevin Green) 
    
    
14. UNIX Tutorial for Beginners 
    
    
15. The Synopsys Design Compiler introductory document prepared by Li Li is here (pdf) . 
    The source files used in the example of this document is here (tarred and gzipped file) . 
    Restore the above file using commands: 
    "gunzip bcd4to7seg.tar.gz" 
    "tar -xvf bcd4to7seg.tar" 
    NOTE: After the above commands are executed, you will have the source VHDL files in a sub-dir. called "files"; so make sure you do NOT already have such a sub-directory where you have copied the bcd4to7seg.tar.gz file. 
    
    
16. The Synopsys Design Vision introductory document prepared by Soumya Banerjee is here (pdf) . 
    The VHDL source files used in the two examples of this document are: ck1.vhd and fsm.vhdl 
    

Messages:

1. Final Exam Syllabus: 
   1) Basics of behavioral, dataflow and structural VHDL descriptions. 
   2) Timing issues: delays, simulation time, timing diagrams, signals vs. variables. 
   3) D&C based design of combinational circuits. 
   4) FSM design and behavioral VHDL description. 
   5) FSM Controller for datapaths. 
   6) Sequential multiplication and division and proofs of correctness. 
   7) Synthesis. 
   
   
2. Sample Finals: 
   (1) pdf 
   (2) pdf 
   (3) pdf 
   (4) pdf 
   (5) pdf 
   Notes: 
   (a) The only synthesis problem among the above exams is in the first one (from S'11). 
   (b) The pipelining aspect in the pipelining + FSM controller problems in the 2nd sample final (F'01)is not there in your final exam syllabus (but the FSM controller and module communication aspect is). 
   
   
   
3. Lab 7 -- due May 2: pdf . 
   Note: In the lab above replace Design Compiler (DC) w/ Design Vision (DV). 
   Input files and packages for Lab 7: 
   (1) Binary Input file: txt . 
   (2) Read-write example vhdl file: vhdl file . 
   (3) Read-write package to be included in the test bench file: vhdl file .
   (4) Example files for "read_write" entity above: (a) txt . 
   (b) txt . 
   
   
   
4. Lab 6 -- Part I due April 18, Part II due April 22: pdf . 
   For Part I: Test bench and test control signals file 
   
   
5. Lab 5 -- due April 8): pdf . 
   
   
6. The midterm will be held "electronically" and by class consensus on Sun 3/24 7pm-10pm. 
   
   Major Midterm topics: 
   1) Basics of behavioral, dataflow and structural VHDL descriptions. 
   2) Timing issues: delays, simulation time, timing diagrams, signals vs variables. 
   3) Concepts in decomposing an architecture into multiple processes. 
   4) FSM design and behavioral VHDL description. 
   5) Generate statements -- especially, the use of generate statements to provide structural description of tree-like circuits. 
   6) Divide-&-Conquer based designs. 
   
   
   
7. Sample Midterms: Qs & solutions: 
   1) Fall 2006: pdf . 
   2) Spring 2006: pdf . 
   3) Fall 2005: pdf 
   
   
8. Lab 4 -- due March 14): pdf . 
   
   
9. Lab 3 -- (part 1 due Feb. 21, part 2 due Feb. 28): pdf . 
   TB for part 2 . 
   
   
10. Lab 2 -- due Thurs. Feb. 14. pdf . 
    Test Bench for Lab 2: txt . 
    Package"rnd2" used in the TB: txt . 
    Copy this package (the file) to your lab directory, for this lab (e.g., "Lab2"), and then parse-and-compile (i.e., use "vhdlan" followed by "vcs") it in the "work" sub-directory for this lab before compiling the TB. This is similar to first parsing-compiling the components of a structural (or mixed) arch. description before compiling the corresponding entity-architecture description that uses (i.e., instantiates) these components. 
    
    
11. Lab 1 -- corrected design due Thurs. Jan. 31 (end of lab session), complete lab report due to TA on Mon. Feb. 4. pdf . 
    Codes for Lab 1: tarfile . 
    Untar the tar file on a Unix machine using the command "tar -xvf lab1.tar". 
    The files are also individually available at: file_dir with the following file names (append the file names to the above URL of the directory following the last '/' in the URL): 
    dec2to4_behav_delay.vhdl, my_and_delay.vhdl, dec2to4_flow_delay.vhdl, my_not_delay.vhdl, dec2to4_struct_delay.vhdl, tb2-4.vhdl, dec3to8_mixed_delay.vhdl, tb3-8.vhdl, dec3to8_struct_delay.vhdl 
    
    
12. For the 1st lab attendance on Thurs Jan. 17: Get from item 12 above, the instructions for setting up your ECE computer account properly for running Synopsys tools and then for running these tools on a simple example. 
    
    
13. Reading Assignment for week 2-3 from the reference text (can do from any logic design text; sections provided for the reference text---Digital Logic Circuit Analysis and Design, V.P. Nelson, et al., Prentice Hall, 1995.):
    1. Chapter 1 of text.
    2. Introduction to logic design: [0.1-0.2] from ref. text. 
       
    3. Number Systems and Codes:} [1.1-1.2] from ref. text. 
       
    4. Logic gates, synthesis of logic circuits using gates: [2.3-2.4.1, 2.5-2.6] from ref. text. 
       

http://www.ece.uic.edu/~dutt/courses/ece368/ece368.html

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